/**************************
//  CRC5 module testbench
//  Date 2014 Feb 19
//  Authur WU
//  Synchronous preset
**************************/

module rfid_crc16_tb();
reg [23:0] crc16_input;
reg clk;
reg preset;

wire [15:0] crc16_output;

rfid_crc16 DUT 
(
  .crc16_input (crc16_input),
  .clk (clk),
  .preset (preset),
  .crc16_output (crc16_output)
                     );
always #1 clk<=~clk;
initial
 begin
 clk<=0; preset=1;crc16_input=0;
  #2      preset=0;crc16_input=24'he67c18;
  #2      preset=1;crc16_input=0;
  #2      preset=0;crc16_input=24'h1a528b;
  #2      preset=1;crc16_input=0;
  #2      preset=0;crc16_input=24'h349727;
  #2      preset=1;crc16_input=0;
  #2      preset=0;crc16_input=24'hb2669;
  end
endmodule